The present invention relates to data processors, and more particularly to a data processor architecture and instruction format for increased efficiency.
In data processing integrated circuits there is a trade-off between programmability and semiconductor area. In particular in the digital signal processing (DSP) area, a general purpose DSP processor may require a large amount of semiconductor area which is used for address generation, instruction decoding and sequencing, and data buffering. Alternatively, a hardware customized DSP may be small in semiconductor area but is usually lacking the flexibility provided by a general purpose DSP processing. A new data processor architecture and instruction format that better balances the programmability vs. semiconductor area trade-off would be valuable.